The present disclosure relates to a clock control circuit and a voltage pumping device using the same, and more particularly to a clock control circuit and a voltage pumping device using the same which are capable of achieving an enhancement in pumping efficiency.
Generally, a DRAM is a random access memory capable of writing or reading data to/from memory cells each consisting of one transistor and one capacitor. Since such a DRAM uses an NMOS transistor for the transistor of each memory cell, it also includes a voltage pumping device for driving word lines, taking into consideration a voltage loss caused by a threshold voltage Vt, in order to generate a voltage higher than a sum of an external supply voltage Vdd and the threshold voltage Vt (Vdd+Vt).
That is, in order to turn on the NMOS transistor mainly used for each DRAM memory cell, it is necessary to apply, to the gate of the NMOS transistor, a voltage higher than a source voltage by the threshold voltage Vt. In detail, since the maximum voltage applicable to the DRAM is limited to the level of the external supply voltage Vdd, a voltage boosted to a level corresponding to “Vdd+Vt” or higher should be applied to the gate of the NMOS transistor, in order to enable a voltage of a full Vdd level to be read from a cell or a bit line or to be written on the cell or bit line.
Recently, much effort has been conducted in semiconductor device fields, in order to achieve various improvements for reduction of power consumption. In particular, various research has been conducted to reduce power consumption in a self-refresh mode of a DRAM semiconductor device. The current consumed for a self-refresh time to store data in a memory cell during a self-refresh operation is referred to as “self-refresh current”. In order to reduce the self-refresh current, it is necessary to increase the self-refresh period. This may be achieved by increasing the time, for which the memory cell sustains data, namely, a data retention time. One method for increasing the data retention time is to increase the back-bias voltage applied to the transistor of each memory cell. In accordance with this method, the back-bias voltage VBB output from a voltage pumping device after being pumped is supplied to each cell transistor at an increased level in a self-refresh mode, as compared to those in other modes. Accordingly, the off leakage current of the cell transistor can be reduced, so that the data retention time can be increased.
As can be seen from the above description, a high voltage VPP is used to drive word lines of a DRAM, whereas the back-bias voltage VBB is applied to the transistor of each memory cell of the DRAM, in order to reduce self-refresh current. The high voltage VPP and back-bias voltage VBB are generated from a voltage pumping device which includes an oscillator and a voltage pump. The voltage pump of the voltage pumping device receives a clock generated from the oscillator, and pumps the high voltage VPP and back-bias voltage VBB, using a method for boosting a voltage at a floated node in accordance with a clock toggling effect and a capacitor coupling effect. In this case, a MOS transistor is used for a switch for floating the node.
In this case, however, a voltage loss corresponding to the threshold voltage is generated due to the characteristics of the MOS transistor, thereby causing a degradation in the efficiency of the voltage pump. Furthermore, the threshold voltage of the MOS transistor is gradually increased due to a body effect. For this reason, when the supply voltage is lowered, it is more difficult to overcome the voltage loss corresponding to the threshold voltage and to pump each of the high voltage VPP and back-bias voltage VBB to a desired level.